In a processing system that supports paged virtual memory, data may be specified using virtual addresses (also referred to as “effective” or “linear” addresses) that occupy a virtual address space of the processing system. The virtual address space may typically be larger than the size of the actual physical memory in the system. The operating system in the processing system may manage the physical memory in fixed size blocks called pages.
To translate virtual page addresses into physical page addresses, the processing system may search page tables stored in the system memory, which may contain the necessary address translation information. A page table may typically be rather large in size, since it may contain a list of all the physical page addresses for all the virtual page addresses generated by the processing system. Also, page table searches (or “page table walks”) may involve memory accesses, which may be time-consuming.
The processing system may therefore perform address translation using one or more translation lookaside buffers (TLBs), which may typically contain a subset of the entries in the page table. A TLB is an address translation cache, i.e. a small cache that stores recent mappings from virtual addresses to physical addresses. The processing system may cache a physical address in the TLB, after performing a page table search and an address translation. A TLB may typically contain a plurality of TLB entries, each TLB entry containing a virtual page address and a corresponding physical page address.
When a TLB receives a virtual page address, the TLB may search its entries to see if any of the cached virtual page addresses in any of these entries match the received virtual page address. If the virtual page address presented to a TLB does match a virtual page address stored in any of the TLB entries, a TLB “hit” may occur; otherwise, a TLB “miss” may occur. Because each TLB lookup consumes power and computer time, reducing the frequency of TLB accesses may be desirable.
A TLB may also store information regarding one or more memory attributes, in addition to information about virtual-to-physical address translations. These memory attributes may, for example, include protection characteristics of memory entries, such as read/write/execute permissions. The memory attributes cached in a TLB may be accessed before, or in parallel with, the access to the memory cache.
Storing these memory attributes in the TLB, in addition to storing virtual-to-physical address translation information, may increase the number of bits required to be cached in each TLB entry. The more bits that have to be accessed, the slower the lookup in the TLB becomes, and the more power it consumes.